Digital Systems Testing And Testable | Design Solution

Digital Systems Testing and Testable Design: Bridging Reliability and Complexity

13. Case Study Example (Concise)

Assume an SoC with 1M gates, 200k sequential elements, and 512 KB embedded memory: digital systems testing and testable design solution

• Fault Models: The industry standard remains the Stuck-At Fault Model (S-A-0 and S-A-1), which assumes a permanent logical value at a node. While conceptually simple, it effectively covers many physical defects.
• Advanced Fault Models: As geometry shrinks, new failure modes have emerged. Modern testing now incorporates Path Delay Faults and Transition Faults to catch timing defects (speed failures) that static voltage tests miss. Bridging faults (shorts between adjacent lines) have also become critical in deep sub-micron technologies.

To solve the visibility gap, engineers embed dedicated "test hardware" directly into the silicon: Fault Models: The industry standard remains the Stuck-At

1. Scan chains: A series of flip-flops connected in a chain to facilitate scan testing.
2. Test points: Additional logic added to the system to facilitate testing.
3. Boundary scan: A technique for testing the inputs and outputs of a system.

The cost of testing is a major factor in semiconductor manufacturing. Every second a chip spends on an Automatic Test Equipment (ATE) machine costs money. To solve the visibility gap, engineers embed dedicated

: A technique used to reduce testing time by grouping multiple faults that can be detected by the same test vector. Springer Nature Link 3. Design for Testability (DFT) Solutions