Synopsys Timing Constraints And Optimization User Guide 2021 -

Post Option 1: Professional & Educational

  • Leakage vs. Dynamic: The engine now uses set_cellular_leviathan thresholds to swap high-Vt cells with low-Vt cells only on critical paths.
  • Clock Gating: The guide introduces set_clock_gating_style with -sequential_cell latch and -minimum_bitwidth 3. It warns that clock gating on fewer than 3 flops increases power due to the gating logic overhead.
  • Operand Isolation: For low-power modes (sleep), the guide details how set_operand_isolation_style removes switching power from idle datapaths without breaking timing.

The "Don't Do This" Section (Hidden Gems)

Buried in Chapter 6 ("Optimizing for High Speed") is a warning that saves countless ECO cycles: synopsys timing constraints and optimization user guide 2021

  • Clock period: 10 ns.
  • Input delay: 3 ns.
  • Output delay: 2 ns.